Phase-locked loop ("PLL") circuits are widely used in many fields, and can be used in any field suitable for integration of high frequency circuits. In particular, PLL circuits are used in various signal processing circuits, such as AM and FM radios, televisions, wireless communication equipment, frequency synthesizers, and multiplex stereo demodulating circuits. In general, a PLL circuit is a feedback loop in which the frequency and phase of a signal produced by a variable oscillator is locked to that of a reference signal. A PLL circuit can be used for demodulating a baseband signal from a frequency-modulated carrier wave. A basic PLL circuit includes a phase comparator and a voltage controlled oscillator. In operation, the phase comparator compares a modulated incoming signal with the output of the voltage controlled oscillator, and the output of the phase comparator controls the oscillation frequency of the voltage controlled oscillator.
FIG. 11 is a block diagram of a conventional digital PLL circuit. As shown, a reference clock signal is supplied to a phase comparator 74, and the output of the phase comparator is supplied to a delay control circuit 73. A variable delay circuit 76 receives the output of the delay control circuit 73, and the output of the variable delay circuit is supplied to an inverter 77. The output of the inverter 77 is fed back to the variable delay circuit 76 so that the variable delay circuit and the inverter form a ring oscillator. The output signal from the ring oscillator (i.e., the inverter) is used as an output clock signal and is also supplied to the phase comparator 74 for comparison with the reference clock signal. The delay control circuit 73 controls the variable delay circuit 76 based on the output of the phase comparator 74 so that the reference clock signal and the output clock signal coincide in phase.
Typically, the variable delay circuit 76 is formed of a string of inverters, and the value of the delay is varied by changing the number of connected inverters. However, relying only upon changes in the number of connected inverters produces a circuit having values of delay that are only roughly controllable. If variable load capacitance circuits (including capacitors) are connected to the output of an inverter, the number of connected capacitors can be changed to vary the output load capacitance of the inverter. This allows more precise control of the delay value, and thus, a higher accuracy digital PLL circuit can be obtained. In such a circuit, the delay control circuit 73 controls the number of connection stages and the output load capacitance of the inverters of the variable delay circuit 76 on the basis of the output from the phase comparator 74.
However, in the conventional digital PLL circuit described above, there exists a drawback in that designing the delay control circuit 73 to lock as a PLL circuit is very difficult because the phase comparison output controls the delay control circuit even after the output clock signal has been more accurately controlled by the output load capacitance of the variable delay circuit 76. For example, even when the frequency of the output clock signal coincides with the frequency of the reference clock signal, if the phase of the output clock signal is behind the phase of the reference clock signal, the delay control circuit 73 operates to decrease the delay value of the variable delay circuit 76 in response to the output of the phase comparator 74. In many cases, repeating this operation to make the phases of the two clock signals coincide causes the frequencies of the two signals to not coincide. Then, the delay control circuit 73 operates to establish coincidence in frequency. As a result, these competing operations are repeated and it takes a long time and many repetitions to make both the frequencies and the phases of the two clock signals coincide.
As described above, it is difficult to design the conventional digital PLL circuit, and particularly difficult to design the delay control circuit, so as to ensure that the output clock signal and the reference clock signal coincide in both phase and frequency. As a result, conventional designs include a complicated structure and an extremely complicated algorithm for controlling the delay control circuit. The conventional digital PLL circuit also suffers from another drawback in that, even after the PLL circuit is locked, the delay control circuit modifies the delay value of the variable delay circuit when even a slight phase shift occurs. This causes the frequency of the output clock signal to change, and thus, increases the amount of jitter in the signal.